IRIS
RE, MARCO
 Distribuzione geografica
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Continente #
NA - Nord America 23.000
EU - Europa 2.176
AS - Asia 1.194
SA - Sud America 11
OC - Oceania 10
AF - Africa 6
Continente sconosciuto - Info sul continente non disponibili 6
Totale 26.403
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Nazione #
US - Stati Uniti d'America 22.985
SG - Singapore 606
IT - Italia 476
CN - Cina 363
IE - Irlanda 337
DE - Germania 314
UA - Ucraina 283
RU - Federazione Russa 175
SE - Svezia 134
FR - Francia 126
FI - Finlandia 96
GB - Regno Unito 94
KR - Corea 78
PL - Polonia 70
IN - India 53
KG - Kirghizistan 33
NL - Olanda 23
AT - Austria 22
JP - Giappone 19
CA - Canada 14
AU - Australia 10
VN - Vietnam 8
ES - Italia 7
EU - Europa 6
PE - Perù 6
TR - Turchia 6
AR - Argentina 5
BE - Belgio 4
CH - Svizzera 4
IR - Iran 4
EG - Egitto 3
HK - Hong Kong 3
IL - Israele 3
KZ - Kazakistan 3
RO - Romania 3
UZ - Uzbekistan 3
GR - Grecia 2
IQ - Iraq 2
LB - Libano 2
MY - Malesia 2
ZA - Sudafrica 2
AE - Emirati Arabi Uniti 1
BA - Bosnia-Erzegovina 1
BD - Bangladesh 1
HU - Ungheria 1
ID - Indonesia 1
JO - Giordania 1
LK - Sri Lanka 1
NO - Norvegia 1
PK - Pakistan 1
RS - Serbia 1
SC - Seychelles 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TT - Trinidad e Tobago 1
Totale 26.403
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Città #
Houston 6.064
Woodbridge 5.981
Wilmington 5.756
Fairfield 820
Chandler 576
Singapore 544
Ann Arbor 481
Ashburn 345
Seattle 337
Dublin 331
Cambridge 280
Medford 245
Jacksonville 234
New York 212
Dearborn 172
Rome 155
Santa Clara 145
Beijing 135
Lawrence 119
Zhengzhou 99
Kraków 67
Menlo Park 48
San Diego 48
Helsinki 45
Palo Alto 41
Moscow 39
Munich 27
Shanghai 21
Mülheim 20
Milan 19
Seoul 19
Marano Di Napoli 17
Nuremberg 16
Norwalk 15
Falls Church 14
London 14
Los Angeles 14
Del Norte 12
Hefei 12
Verona 11
Huskvarna 10
Kunming 10
Nanjing 10
Palakkad 10
University Park 10
Chengdu 9
Redwood City 9
Leawood 8
Mountain View 8
Augusta 7
Hangzhou 7
Naples 7
San Mateo 7
Vienna 7
Cusco 6
Dong Ket 6
Madrid 6
Salt Lake City 6
Toronto 6
Atlanta 5
Bologna 5
Córdoba 5
Hebei 5
Jena 5
Nanchang 5
Ottawa 5
Padova 5
Saint Petersburg 5
Amsterdam 4
Bengaluru 4
Guangzhou 4
Guastalla 4
Indiana 4
Kochi 4
Las Vegas 4
Massy 4
Paris 4
Sant'angelo Romano 4
Shenyang 4
Tokyo 4
Zagarolo 4
Almaty 3
Altenberge 3
Boardman 3
Boulogne-Billancourt 3
Brugherio 3
Catania 3
Chicago 3
Cogliate 3
Council Bluffs 3
Hounslow 3
Nepi 3
Phoenix 3
Prescot 3
Rancho Cucamonga 3
Ravenna 3
Redmond 3
Saint Paul 3
San Severo 3
Torino 3
Totale 23.853
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Nome #
Improved large-signal model for vacuum triodes 489
Spiking neural networks based on LIF with latency: Simulation and synchronization effects 439
Arithmetic/logic blocks for fine-grained reconfigurable units 430
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams 430
Multiple constant multiplication through residue number system 428
A reconfigurable functional unit for modular operations 427
Synaptic behaviour in ZnO-rGO composites thin film memristor 423
A full-adder based reconfigurable architecture for fine grain applications: ADAPTO 422
Concurrent Error Detection in Reed ndash;Solomon Encoders and Decoders 420
Power efficient design of parallel/serial FIR filters in RNS 418
A self-checking cell logic block for fault tolerant FPGAs 414
System-on-chip oriented fault-tolerant sequential systems implementation methodology 412
Error correction codes for SEU and SEFI tolerant memory systems 410
Design of large polyphase filters in the quadratic residue number system 409
Development of a dynamic routing system for a fault tolerant solid state mass memory 407
VLSI implementation of reconfigurable cells for RFU in embedded processors 405
Implementation of the AES algorithm using a reconfigurable functional unit 401
Fine-grain reconfigurable functional unit for embedded processors 401
Error detection in signed digit arithmetic circuit with parity checker [adder example] 399
Hardware design of LIF with Latency neuron model with memristive STDP synapses 399
Localization of faults in radix-n signed digit adders 397
A fault tolerant hardware based file system manager for solid state mass memory 395
High performance bit-stream decompressor for partial reconfigurable FPGAs 395
Hardware implementation of MPEG analysis and deblocking for video enhancement 394
Optimized implementation of RNS FIR filters based on FPGAs 394
Speed-up of RISC processor computation using ADAPTO 393
Karatsuba implementation of FIR filters 393
A fault-tolerant solid state mass memory for highly reliable instrumentation 390
Analysis of Errors and Erasures in Parity Sharing RS Codecs 387
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving 384
Compressive sensing spectrum analysis for space autonomous radio receivers 379
Comparative Evaluation of Designs for Reliable Memory Systems 377
Event-driven simulation of continuous-time neural networks 377
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit 375
Design of a totally self checking signature analysis checker for finite state machines 374
Truncated multipliers through power-gating for degrading precision arithmetic 372
Degrading precision arithmetic for low power signal processing 371
Continuous-time spiking neural networks: general paradigm and event-driven simulation 368
AudiNect: an aid for the autonomous navigation of visually impaired people, based on virtual interface 368
FPGA implementation of a low-area/high-SFDR DDFS architecture 365
Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] 361
ZnO-rGO composite thin film resistive switching device: emulating biological synapse behavior 361
Partial reconfiguration in the implementation of autonomous radio receivers for space 360
Fully digital intensity modulated LIDAR 356
A Comparative Evaluation of Designs for Reliable Memory Systems 354
Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor 346
Error detection in addition chain based ECC point multiplication 344
Fault tolerant solid state mass memory for space applications 343
A signed digit adder with error correction and graceful degradation capabilities 337
Degrading precision arithmetics for low-power FIR implementation 332
null 323
Imprecise arithmetic for low power image processing 314
Design of a fault tolerant solid state mass memory 289
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility 215
Comparison between trigonometric and traditional DDS, in 90 nm technology 209
Energy consumption saving in embedded microprocessors using hardware accelerators 183
FPGA implementation of a channelizer with 2048 channels utilizing USRP-SDR platform for satellite communications 164
Memristive and memory impedance behavior in a photo-annealed ZnO–rGO thin-film device 161
AW-SOM, an algorithm for high-speed learning in hardware self-organizing maps 160
An efficient hardware implementation of reinforcement learning: The q-learning algorithm 158
Q-RTS: A real-time swarm intelligence based on multi-agent Q-learning 158
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures 153
Compressive sensing reconstruction for complex system: A hardware/software approach 152
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker 152
Approximated computing for low power neural networks 151
Analog chain calibration in Digital Beam-Forming applications 151
N-dimensional approximation of Euclidean distance 147
Comparison of low-complexity algorithms for real-time QRS detection using standard ECG database 145
A wireless sensor node based on microbial fuel cell 145
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications 142
A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements 140
Robust throughput boosting for low latency dynamic partial reconfiguration 134
IP generator tool for efficient hardware acceleration of self-organizing maps 134
A hardware framework for on-chip FPGA acceleration 132
A Power Efficient Digital Front-End for Cognitive Radio Systems 130
An FPGA-based multi-agent reinforcement learning timing synchronizer 127
RNS applications in digital signal processing 127
Hardware prototyping and validation of a W-ΔDOR digital signal processor 125
null 123
Flexible channel extractor for wideband systems based on polyphase filter bank 122
Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning 114
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation 111
Comparison and implementation of variable fractional delay filters for wideband digital beamforming 107
Twenty years of research on RNS for DSP: Lessons learned and future perspectives 105
Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT 96
Design space exploration based methodology for residue number system digital filters implementation 95
Efficient Digital Implementation of a Multirate-based Variable Fractional Delay Filter for Wideband Beamforming 74
M-PSK demodulator with joint carrier and timing recovery 71
A Parallel hardware implementation for 2D hierarchical clustering based on fuzzy logic 61
ADAPTO: Full-adder based reconfigurable architecture for bit level operations 57
Characterization of RNS multiply-add units for power efficient DSP 53
FPGA implementation of a low-power QRS extractor 52
A reinforcement learning-based QAM/PSK symbol synchronizer 50
An Action-selection policy generator for reinforcement learning hardware accelerators 47
Comparison of jamming excision methods for direct sequence/spread spectrum (DS/SS) modulated signal 46
A ZnO-rGO composite thin film discrete memristor 46
Digital signal processing accelerator for RISC-V 45
A Q-learning based PSK symbol synchronizer 42
A software defined radio architecture for a regenerative on-board processor 42
A M-PSK Timing Recovery Loop Based on Q-Learning 40
Totale 25.845
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Categoria #
all - tutte 65.249
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 65.249
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20204.713 0 0 0 0 515 691 567 500 740 633 556 511
2020/20214.997 583 581 490 647 506 573 575 547 158 107 168 62
2021/20221.312 46 112 23 53 42 106 46 48 292 66 47 431
2022/20231.448 148 159 80 117 130 328 123 74 117 13 112 47
2023/2024771 65 17 30 29 70 260 57 34 31 38 59 81
2024/20251.437 103 679 422 170 63 0 0 0 0 0 0 0
Totale 26.816