Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R. (2010). Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor. In Conference record of the forty fourth asilomar conference on signals, systems and computers (ASILOMAR), 2010 (pp.1279-1283). IEEE [10.1109/ACSSC.2010.5757737].

Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor

CARDARILLI, GIAN CARLO;Di Nunzio, L;RE, MARCO;
2010-01-01

Conference record of the forty fourth asilomar conference on signals, systems and computers (ASILOMAR)
Monterey, CA, USA
2010
IEEE
Rilevanza internazionale
contributo
2010
Settore ING-INF/01 - ELETTRONICA
English
Altera NIOS-II embedded processor;Altera-Stratix FPGA;BMU;VHDL;bit manipulation unit;butterfly nets;custom logic feature;instruction set architecture;inverse butterfly nets;microprocessor chip;word length 32 bit;embedded systems;field programmable gate arrays;hardware description languages;hypercube networks;instruction sets;microprocessor chips;
Intervento a convegno
Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R. (2010). Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor. In Conference record of the forty fourth asilomar conference on signals, systems and computers (ASILOMAR), 2010 (pp.1279-1283). IEEE [10.1109/ACSSC.2010.5757737].
Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Re, M; Lee, R
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/23941
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