IRIS

Cardarilli, G.c., Di Nunzio, L., Re, M. (2008). A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. In 15th IEEE International conference on electronics, circuits and systems, 2008. ICECS 2008. (pp.1304-1307). IEEE [10.1109/ICECS.2008.4675099].

A full-adder based reconfigurable architecture for fine grain applications: ADAPTO

CARDARILLI, GIAN CARLO;Di Nunzio, L;RE, MARCO
2008-01-01
15th IEEE International conference on electronics, circuits and systems, 2008. ICECS 2008.
Malta
2008
IEEE
Rilevanza internazionale
contributo
2008
Settore ING-INF/01 - ELETTRONICA
English
adder-based dynamic architecture for processing tailored operators;clock cycle;digital signal processing;full-adder;hardware reconfiguration;instruction execution;interconnect network;microprocessor;reconfigurable architecture;reconfigurable unit;adders;clocks;digital signal processing chips;multiprocessor interconnection networks;reconfigurable architectures;
Intervento a convegno
Cardarilli, G.c., Di Nunzio, L., Re, M. (2008). A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. In 15th IEEE International conference on electronics, circuits and systems, 2008. ICECS 2008. (pp.1304-1307). IEEE [10.1109/ICECS.2008.4675099].
Cardarilli, Gc; Di Nunzio, L; Re, M
02 - Intervento a convegno
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/27078
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