Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors. © 2012 IEEE.

Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R. (2012). Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp.1457-1459). Piscataway - NJ : IEEE [10.1109/ACSSC.2012.6489268].

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving

CARDARILLI, GIAN CARLO;Di Nunzio, L;RE, MARCO;
2012-01-01

Abstract

Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors. © 2012 IEEE.
Asilomar Conference on Signals, Systems and Computers 2012
Asilomar, CA, USA
2012
IEEE
Rilevanza internazionale
su invito
nov-2012
2012
Settore ING-INF/01 - ELETTRONICA
English
Reconfigurable systems; High performance computing; Microprocessors
http://www.scopus.com/inward/record.url?eid=2-s2.0-84876206961&partnerID=40&md5=c160586eb75c87f483a1e2cbe22f5ebc
Intervento a convegno
Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R. (2012). Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp.1457-1459). Piscataway - NJ : IEEE [10.1109/ACSSC.2012.6489268].
Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Re, M; Lee, R
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/104292
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