Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors. © 2012 IEEE.
Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R. (2012). Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp.1457-1459). Piscataway - NJ : IEEE [10.1109/ACSSC.2012.6489268].
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving
CARDARILLI, GIAN CARLO;Di Nunzio, L;RE, MARCO;
2012-01-01
Abstract
Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors. © 2012 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
