In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.

Acciarito, S., Cardarilli, G.C., Cristini, A., Di Nunzio, L., Fazzolari, R., Khanal, G., et al. (2017). Hardware design of LIF with Latency neuron model with memristive STDP synapses. INTEGRATION, 59, 81-89 [10.1016/j.vlsi.2017.05.006].

Hardware design of LIF with Latency neuron model with memristive STDP synapses

ACCIARITO, SIMONE;CARDARILLI, GIAN CARLO;CRISTINI, ALESSANDRO;DI NUNZIO, LUCA;FAZZOLARI, ROCCO;KHANAL, GAURAVMANI;RE, MARCO;SUSI, GIANLUCA
2017

Abstract

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.
Pubblicato
Rilevanza internazionale
Articolo
Esperti anonimi
Settore ING-IND/31 - Elettrotecnica
Settore ING-INF/01 - Elettronica
English
Leaky integrate-and-fire with latency (LIFL); neuron; synapse; STDP; Memristor; neuromorphic system; analog VLSI
Acciarito, S., Cardarilli, G.C., Cristini, A., Di Nunzio, L., Fazzolari, R., Khanal, G., et al. (2017). Hardware design of LIF with Latency neuron model with memristive STDP synapses. INTEGRATION, 59, 81-89 [10.1016/j.vlsi.2017.05.006].
Acciarito, S; Cardarilli, Gc; Cristini, A; DI NUNZIO, L; Fazzolari, R; Khanal, G; Re, M; Susi, G
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/2108/189481
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