It is well known that the Residue Number System (RNS) provides an efficient implementation of parallel FIR filters especially when the filter order and the dynamic range are high. The two main drawbacks of RNS, need of converters and coding overhead, make a serialized implementation of the FIR filter potentially disadvantageous with respect to filters implemented in the conventional number systems. In this work, we show a number of solutions which demonstrate that the power efficiency of RNS FIR filters implemented serially is maintained in ASIC technology, while in modern FPGA technology RNS implementations are less efficient
Petricca, M., Albicocco, P., Cardarilli, G.c., Nannarelli, A., Re, M. (2012). Power efficient design of parallel/serial FIR filters in RNS. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp.1015-1019). Piscataway - NJ : IEEE [10.1109/ACSSC.2012.6489171].
Power efficient design of parallel/serial FIR filters in RNS
CARDARILLI, GIAN CARLO;RE, MARCO
2012-01-01
Abstract
It is well known that the Residue Number System (RNS) provides an efficient implementation of parallel FIR filters especially when the filter order and the dynamic range are high. The two main drawbacks of RNS, need of converters and coding overhead, make a serialized implementation of the FIR filter potentially disadvantageous with respect to filters implemented in the conventional number systems. In this work, we show a number of solutions which demonstrate that the power efficiency of RNS FIR filters implemented serially is maintained in ASIC technology, while in modern FPGA technology RNS implementations are less efficientI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
