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RE, MARCO

RE, MARCO  

Dipartimento di Ingegneria Elettronica  

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Risultati 1 - 20 di 132 (tempo di esecuzione: 0.035 secondi).
Data di pubblicazione Titolo Autore(i) Tipo File
1-gen-2005 A Comparative Evaluation of Designs for Reliable Memory Systems Cardarilli, Gc; Lombardi, F; Ottavi, M; Pontarelli, S; Re, M; Salsano, A Articolo su rivista
1-gen-2003 A fault tolerant hardware based file system manager for solid state mass memory Cardarilli, Gc; Ottavi, M; Pontarelli, S; Re, M; Salsano, A Intervento a convegno
1-gen-2004 A fault-tolerant solid state mass memory for highly reliable instrumentation Cardarilli, Gc; Ottavi, M; Pontarelli, S; Re, M; Salsano, A Intervento a convegno
1-gen-2015 A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration Cardarilli, Gc; Di Carlo, L; Nannarelli, A; Pandolfi, Fm; Re, M Intervento a convegno
1-gen-2008 A full-adder based reconfigurable architecture for fine grain applications: ADAPTO Cardarilli, Gc; Di Nunzio, L; Re, M Intervento a convegno
1-gen-2016 A hardware framework for on-chip FPGA acceleration Lomuscio, A; Cardarilli, Gc; Nannarelli, A; Re, M Intervento a convegno
1-gen-2023 A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning Canese, L; Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Re, M; Spano, S Intervento a convegno
1-gen-2022 A M-PSK Timing Recovery Loop Based on Q-Learning Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Giardino, D; Guadagno, M; Re, M; Spano, S Intervento a convegno
1-gen-2017 A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Gerardi, L; Re, M; Campolo, G; Cascone, D Intervento a convegno
1-gen-2008 A novel error detection and correction technique for RNS based FIR filters Pontarelli, S; Cardarilli, Gc; Re, M; Salsano, A Intervento a convegno
1-gen-2021 A Parallel hardware implementation for 2D hierarchical clustering based on fuzzy logic Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Panella, M; Re, M; Rosato, A; Spano, S Articolo su rivista
1-gen-2018 A Power Efficient Digital Front-End for Cognitive Radio Systems Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Nannarelli, A; Re, M Intervento a convegno
1-gen-2021 A pseudo-softmax function for hardware-based high speed image classification Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Giardino, D; Nannarelli, A; Re, M; Spano, S Articolo su rivista
1-gen-2019 A Q-learning based PSK symbol synchronizer Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Giardino, D; Matta, M; Re, M; Silvestri, F; Spano, S Intervento a convegno
1-giu-2014 A reconfigurable functional unit for modular operations Cardarilli, Gc; DI NUNZIO, L; Fazzolari, R; Pontarelli, S; Re, M Contributo in libro
1-gen-2019 A reinforcement learning-based QAM/PSK symbol synchronizer Matta, M; Cardarilli, Gc; Di Nunzio, L; Fazzolari, R; Giardino, D; Nannarelli, A; Re, M; Spano, S Articolo su rivista
1-gen-2024 A RISC-V Hardware Accelerator for Q-Learning Algorithm Angeloni, D; Canese, L; Cardarilli, Gc; Di Nunzio, L; Re, M; Spano, S Intervento a convegno
1-gen-2002 A self-checking cell logic block for fault tolerant FPGAs Pontarelli, S; Cardarilli, Gc; Leandri, A; Ottavi, M; Re, M; Salsano, A Intervento a convegno
1-gen-2004 A signed digit adder with error correction and graceful degradation capabilities Cardarilli, Gc; Ottavi, M; Pontarelli, S; Re, M; Salsano, A Intervento a convegno
1-gen-2008 A software defined radio architecture for a regenerative on-board processor Iacomacci, F; Morlet, C; Autelitano, F; Cardarilli, Gc; Re, M; Petrongari, E; Bogo, G; Franceschelli, M Intervento a convegno