Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

Cardarilli, G.c., Pontarelli, S., Re, M., Salsano, A. (2007). Concurrent Error Detection in Reed ndash;Solomon Encoders and Decoders. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 15(7), 842-846 [10.1109/TVLSI.2007.899241].

Concurrent Error Detection in Reed ndash;Solomon Encoders and Decoders

CARDARILLI, GIAN CARLO;PONTARELLI, SALVATORE;RE, MARCO;SALSANO, ADELIO
2007-01-01

Abstract

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.
2007
Pubblicato
Rilevanza internazionale
Articolo
Sì, ma tipo non specificato
Settore ING-INF/01 - ELETTRONICA
English
Con Impact Factor ISI
RS codes;arithmetic operations;binary representation;concurrent error detection;fault tolerance;self-checking Reed-Solomon decoder architecture;self-checking Reed-Solomon encoder architecture;Galois fields;Reed-Solomon codes;arithmetic codes;decoding;error correction codes;error detection codes;fault tolerance;logic circuits;logic design;
Cardarilli, G.c., Pontarelli, S., Re, M., Salsano, A. (2007). Concurrent Error Detection in Reed ndash;Solomon Encoders and Decoders. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 15(7), 842-846 [10.1109/TVLSI.2007.899241].
Cardarilli, Gc; Pontarelli, S; Re, M; Salsano, A
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/60094
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