When reducing the power dissipation of resource constrained electronic systems is a priority, some precision can be traded-off for lower power consumption. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we apply power-gating to multipliers to obtain a programmable truncated multiplier. The method consists in disabling the least-significant columns of the multiplier by power-gating logic in the partial products generation and accumulation array. © 2013 IEEE.
Albicocco, P., Cardarilli, G.c., Nannarelli, A., Petricca, M., Re, M. (2013). Truncated multipliers through power-gating for degrading precision arithmetic. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp.2172-2176). Piscataway - NJ : IEEE Computer Society [10.1109/ACSSC.2013.6810694].
Truncated multipliers through power-gating for degrading precision arithmetic
CARDARILLI, GIAN CARLO;RE, MARCO
2013-11-01
Abstract
When reducing the power dissipation of resource constrained electronic systems is a priority, some precision can be traded-off for lower power consumption. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we apply power-gating to multipliers to obtain a programmable truncated multiplier. The method consists in disabling the least-significant columns of the multiplier by power-gating logic in the partial products generation and accumulation array. © 2013 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
