High performance bit-stream decompressor for partial reconfigurable FPGAs

In Digital Signal Processing (DSP), Field Programmable Gate Arrays (FPGAs) are becoming ubiquitous for their capability to process massive amount of data in parallel maintaining the flexibility of the software approach. FPGA chips of major vendors also support partial dynamic programming, namely the ability to change the functionality of portions of FPGA while the rest of the functionalities remain active. In this way, partial reconfiguration of the FPGA requires a fast reload of a partial bitstream. To this purpose, an improvement of the reconfiguration speed (with the contemporary reduction of the memory occupancy) is obtained by compressing the bitstreams. High performance on board decompressors are required to speed-up the reconfiguration operation. In this paper a new hardware oriented technique for the bitstream compression and decompression is proposed. This technique maintains good compression factors and correspond to a very simple and fast hardware architecture for the compressor block.