This paper describes the FPGA implementation of a low area and high Spurious Free Dynamic Range (SFDR) Direct Digital Frequency Synthesizer (DDFS). The proposed architecture derives from the one proposed in [1] and fits perfectly in modern FPGA having DSP Blocks and/or embedded multipliers. The DDFS model in [1] was modified in order to reduce further the ROM size by a factor of 2 without worsen the SFDR and was implemented on a XILINX Virtex 5 FPGA. In this work we show that using the proposed hardware architecture, it is possible to reach very high SFDR (more than 157 dB) without impacting on the area occupancy. In fact traditional LUT-based DDFS has an exponential relationship between the ROM size and the number of phase bits. © 2011 IEEE.
Cardarilli, G.c., D'Alessio, M., Di Nunzio, L., Fazzolari, R., Murgia, D., Re, M. (2011). FPGA implementation of a low-area/high-SFDR DDFS architecture. In ISSCS 2011 - International Symposium on Signals, Circuits and Systems, Proceedings (pp.93-96). Piscataway - NJ : IEEE [10.1109/ISSCS.2011.5978667].
FPGA implementation of a low-area/high-SFDR DDFS architecture
CARDARILLI, GIAN CARLO;Di Nunzio, L;RE, MARCO
2011-01-01
Abstract
This paper describes the FPGA implementation of a low area and high Spurious Free Dynamic Range (SFDR) Direct Digital Frequency Synthesizer (DDFS). The proposed architecture derives from the one proposed in [1] and fits perfectly in modern FPGA having DSP Blocks and/or embedded multipliers. The DDFS model in [1] was modified in order to reduce further the ROM size by a factor of 2 without worsen the SFDR and was implemented on a XILINX Virtex 5 FPGA. In this work we show that using the proposed hardware architecture, it is possible to reach very high SFDR (more than 157 dB) without impacting on the area occupancy. In fact traditional LUT-based DDFS has an exponential relationship between the ROM size and the number of phase bits. © 2011 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
