IRIS

Petricca, M., Cardarilli, G.c., Nannarelli, A., Re, M., Albicocco, P. (2010). Degrading precision arithmetic for low power signal processing. In Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on (pp.1163-1167). IEEE [10.1109/ACSSC.2010.5757713].

Degrading precision arithmetic for low power signal processing

CARDARILLI, GIAN CARLO;RE, MARCO;
2010-01-01
Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
Monterey, CA, USA
2010
Rilevanza internazionale
contributo
2010
Settore ING-INF/01 - ELETTRONICA
English
DSP;carry-chain re-design;clock-gating;digital signal processing system;low power signal processing;power dissipation;precision arithmetic;resource constrained electronic system;carry logic;clocks;digital signal processing chips;low-power electronics;signal processing;
Intervento a convegno
Petricca, M., Cardarilli, G.c., Nannarelli, A., Re, M., Albicocco, P. (2010). Degrading precision arithmetic for low power signal processing. In Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on (pp.1163-1167). IEEE [10.1109/ACSSC.2010.5757713].
Petricca, M; Cardarilli, Gc; Nannarelli, A; Re, M; Albicocco, P
02 - Intervento a convegno
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/23988
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