IRIS
CARDARILLI, GIAN CARLO
 Distribuzione geografica
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Continente #
NA - Nord America 27.416
EU - Europa 2.634
AS - Asia 1.411
SA - Sud America 11
OC - Oceania 10
AF - Africa 7
Continente sconosciuto - Info sul continente non disponibili 7
Totale 31.496
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Nazione #
US - Stati Uniti d'America 27.396
SG - Singapore 736
IT - Italia 549
CN - Cina 416
IE - Irlanda 392
DE - Germania 374
UA - Ucraina 346
RU - Federazione Russa 210
SE - Svezia 189
FR - Francia 157
GB - Regno Unito 125
FI - Finlandia 111
PL - Polonia 91
KR - Corea 88
IN - India 54
KG - Kirghizistan 35
AT - Austria 32
NL - Olanda 22
JP - Giappone 20
CA - Canada 19
BE - Belgio 12
PK - Pakistan 12
VN - Vietnam 12
AU - Australia 10
ES - Italia 7
EU - Europa 7
HK - Hong Kong 6
PE - Perù 6
TR - Turchia 6
CH - Svizzera 5
AR - Argentina 4
IL - Israele 4
UZ - Uzbekistan 4
EG - Egitto 3
IR - Iran 3
KZ - Kazakistan 3
RO - Romania 3
GR - Grecia 2
HU - Ungheria 2
IQ - Iraq 2
LB - Libano 2
MY - Malesia 2
ZA - Sudafrica 2
AE - Emirati Arabi Uniti 1
BA - Bosnia-Erzegovina 1
BD - Bangladesh 1
BO - Bolivia 1
DM - Dominica 1
ID - Indonesia 1
JO - Giordania 1
KW - Kuwait 1
LK - Sri Lanka 1
NO - Norvegia 1
RS - Serbia 1
SC - Seychelles 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TN - Tunisia 1
Totale 31.496
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Città #
Woodbridge 7.241
Houston 7.142
Wilmington 6.732
Fairfield 999
Chandler 661
Singapore 659
Ann Arbor 634
Ashburn 434
Seattle 405
Dublin 386
Cambridge 335
Jacksonville 291
Medford 291
New York 244
Dearborn 227
Rome 181
Santa Clara 171
Beijing 159
Lawrence 140
Zhengzhou 111
Kraków 88
San Diego 60
Menlo Park 55
Helsinki 49
Palo Alto 44
Moscow 43
Munich 30
Mülheim 30
Milan 29
Shanghai 22
Los Angeles 21
London 19
Del Norte 18
Marano Di Napoli 18
Norwalk 18
Nuremberg 18
Seoul 18
Falls Church 15
Hefei 15
Nanjing 15
University Park 14
Islamabad 12
Verona 12
Huskvarna 11
Kunming 11
Redwood City 11
Brussels 10
Palakkad 10
San Mateo 10
Toronto 10
Vienna 10
Chengdu 9
Leawood 8
Mountain View 8
Salt Lake City 8
Augusta 7
Dong Ket 7
Hangzhou 7
Naples 7
Saint Petersburg 7
Boardman 6
Cusco 6
Kilburn 6
Madrid 6
Nanchang 6
Atlanta 5
Bologna 5
Council Bluffs 5
Hebei 5
Indiana 5
Jena 5
Ottawa 5
Padova 5
Phoenix 5
Amsterdam 4
Córdoba 4
Guangzhou 4
Guastalla 4
Jinan 4
Kochi 4
Las Vegas 4
Massy 4
Paris 4
Sant'angelo Romano 4
Shenyang 4
Tokyo 4
Zagarolo 4
Almaty 3
Altenberge 3
Boulogne-Billancourt 3
Brugherio 3
Catania 3
Chicago 3
Chiswick 3
Cogliate 3
Hounslow 3
Islington 3
Modena 3
Nepi 3
Oakland 3
Totale 28.423
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Nome #
Improved large-signal model for vacuum triodes 489
Describing different brain computer interface systems through a unique model: a UML implementation 439
Spiking neural networks based on LIF with latency: Simulation and synchronization effects 439
A New hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility 436
Arithmetic/logic blocks for fine-grained reconfigurable units 430
Bit flip injection in processor-based architectures: a case study 430
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams 430
Multiple constant multiplication through residue number system 428
A reconfigurable functional unit for modular operations 427
Sistemi elettronici tolleranti ai guasti per applicazioni spaziali 427
Synaptic behaviour in ZnO-rGO composites thin film memristor 423
Development of an evaluation model for the design of fault-tolerant solid state mass memory 422
A full-adder based reconfigurable architecture for fine grain applications: ADAPTO 422
Concurrent Error Detection in Reed ndash;Solomon Encoders and Decoders 420
Power efficient design of parallel/serial FIR filters in RNS 418
A self-checking cell logic block for fault tolerant FPGAs 414
System-on-chip oriented fault-tolerant sequential systems implementation methodology 412
Error correction codes for SEU and SEFI tolerant memory systems 410
Design of large polyphase filters in the quadratic residue number system 409
Development of a dynamic routing system for a fault tolerant solid state mass memory 407
VLSI implementation of reconfigurable cells for RFU in embedded processors 405
Implementation of the AES algorithm using a reconfigurable functional unit 401
Fine-grain reconfigurable functional unit for embedded processors 401
Performances evaluation and optimization of brain computer interface systems in a copy spelling task 400
Error detection in signed digit arithmetic circuit with parity checker [adder example] 399
Hardware design of LIF with Latency neuron model with memristive STDP synapses 399
A fault-tolerant 176 GBit solid state mass memory architecture 398
Localization of faults in radix-n signed digit adders 397
A fault tolerant hardware based file system manager for solid state mass memory 395
High performance bit-stream decompressor for partial reconfigurable FPGAs 395
Hardware implementation of MPEG analysis and deblocking for video enhancement 394
Optimized implementation of RNS FIR filters based on FPGAs 394
Speed-up of RISC processor computation using ADAPTO 393
Karatsuba implementation of FIR filters 393
Very efficient VLSI implementation of CNN with discrete templates 390
A fault-tolerant solid state mass memory for highly reliable instrumentation 390
Evaluation of the performances of different P300 based brain-computer interfaces by means of the efficiency metric 388
Analysis of Errors and Erasures in Parity Sharing RS Codecs 387
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving 384
Analysis and evaluations of reliability of reconfigurable FPGAs 382
Compressive sensing spectrum analysis for space autonomous radio receivers 379
Comparative Evaluation of Designs for Reliable Memory Systems 377
Event-driven simulation of continuous-time neural networks 377
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit 375
Design of a totally self checking signature analysis checker for finite state machines 374
Truncated multipliers through power-gating for degrading precision arithmetic 372
Degrading precision arithmetic for low power signal processing 371
Continuous-time spiking neural networks: general paradigm and event-driven simulation 368
FPGA implementation of a low-area/high-SFDR DDFS architecture 365
Efficiency of a BCI system in a visual P300 protocol with different stimulation intervals 363
Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] 361
ZnO-rGO composite thin film resistive switching device: emulating biological synapse behavior 361
Partial reconfiguration in the implementation of autonomous radio receivers for space 360
Evaluating data integrity of memory systems by configurable Markov models 359
Fully digital intensity modulated LIDAR 356
A Comparative Evaluation of Designs for Reliable Memory Systems 354
Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor 346
Error detection in addition chain based ECC point multiplication 344
Fault tolerant solid state mass memory for space applications 343
A signed digit adder with error correction and graceful degradation capabilities 337
Degrading precision arithmetics for low-power FIR implementation 332
null 323
Imprecise arithmetic for low power image processing 314
Design of a fault tolerant solid state mass memory 289
SMARTBENCH: QUANDO LA SICUREZZA NEGLI STABILIMENTI INDUSTRIALI DIVENTA SMART 238
Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links 227
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility 215
Comparison between trigonometric and traditional DDS, in 90 nm technology 209
Energy consumption saving in embedded microprocessors using hardware accelerators 183
Memristive and memory impedance behavior in a photo-annealed ZnO–rGO thin-film device 161
AW-SOM, an algorithm for high-speed learning in hardware self-organizing maps 160
An efficient hardware implementation of reinforcement learning: The q-learning algorithm 158
Q-RTS: A real-time swarm intelligence based on multi-agent Q-learning 157
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures 153
Compressive sensing reconstruction for complex system: A hardware/software approach 152
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker 152
Approximated computing for low power neural networks 151
Analog chain calibration in Digital Beam-Forming applications 151
N-dimensional approximation of Euclidean distance 147
Comparison of low-complexity algorithms for real-time QRS detection using standard ECG database 145
A wireless sensor node based on microbial fuel cell 145
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications 142
A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements 140
Robust throughput boosting for low latency dynamic partial reconfiguration 134
A hardware framework for on-chip FPGA acceleration 132
A Power Efficient Digital Front-End for Cognitive Radio Systems 130
An FPGA-based multi-agent reinforcement learning timing synchronizer 127
RNS applications in digital signal processing 127
Hardware prototyping and validation of a W-ΔDOR digital signal processor 125
null 123
Flexible channel extractor for wideband systems based on polyphase filter bank 122
Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning 114
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation 111
Comparison and implementation of variable fractional delay filters for wideband digital beamforming 107
Twenty years of research on RNS for DSP: Lessons learned and future perspectives 105
Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT 96
Design space exploration based methodology for residue number system digital filters implementation 95
VLSI RNS Implementation of fast IIR filters 88
Efficient Digital Implementation of a Multirate-based Variable Fractional Delay Filter for Wideband Beamforming 74
M-PSK demodulator with joint carrier and timing recovery 71
Totale 29.984
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Categoria #
all - tutte 77.106
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 77.106
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20205.620 0 0 0 0 650 877 710 617 849 720 611 586
2020/20215.641 638 652 548 715 591 646 644 617 189 126 197 78
2021/20221.582 57 134 48 64 46 130 55 52 325 103 57 511
2022/20231.685 178 182 88 136 144 388 141 84 141 16 126 61
2023/2024890 75 21 37 32 79 297 65 36 32 42 84 90
2024/20251.725 123 834 495 204 69 0 0 0 0 0 0 0
Totale 31.969