In this paper the use of Signed Digit (SD) Arithmetic to better exploit some of the architectural characteristic of the last generation FPGAs is presented. The implementation of Radix-4 SD adders, multipliers and Finite Impulse Response (FIR) filters has been carried out to demonstrate that the use of this number system representation optimally fits the 6-input LUT Logic Elements (LEs) of the newest FPGAs architectures. Comparisons of implementations of the same circuits by using 4-input LUT and 6-input LUT based FPGAs have been carried out showing that Radix-4 SD arithmetic is very efficiently implemented in the last generation FPGAS. © 2008 IEEE.
Cardarilli, G.c., Pontarelli, S., Re, M., Salsano, A. (2008). On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp.602-605) [10.1109/ICECS.2008.4674925].
On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs
Cardarilli G. C.;Pontarelli S.;Re M.;Salsano A.
2008-01-01
Abstract
In this paper the use of Signed Digit (SD) Arithmetic to better exploit some of the architectural characteristic of the last generation FPGAs is presented. The implementation of Radix-4 SD adders, multipliers and Finite Impulse Response (FIR) filters has been carried out to demonstrate that the use of this number system representation optimally fits the 6-input LUT Logic Elements (LEs) of the newest FPGAs architectures. Comparisons of implementations of the same circuits by using 4-input LUT and 6-input LUT based FPGAs have been carried out showing that Radix-4 SD arithmetic is very efficiently implemented in the last generation FPGAS. © 2008 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
