We introduce a MATLAB-Simulink software able to generate customizable hardware IP cores for the Reinforcement Learning algorithm called Q-Learning. The tool automatically produces the VHDL code and runs both synthesis and implementation for any AMD-Xilinx FPGA using the Vivado software chain. Our automatic generator relies on the “HDL coder” from Mathworks to produce an efficient hardware accelerator based on the state of the art. The model can be customized by the user according to the desired Q-Matrix size and bit-depth for all the algorithm parameters.
Canese, L., Cardarilli, G.c., Di Nunzio, L., Fazzolari, R., Re, M., Span('o), S. (2023). Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. In Applications in electronics pervading industry, environment and society : APPLEPIES 2022 (pp.242-247). Cham : Springer [10.1007/978-3-031-30333-3_32].
Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators
Canese, L.;Cardarilli, G. C.;Di Nunzio, L.;Fazzolari, R.;
2023-01-01
Abstract
We introduce a MATLAB-Simulink software able to generate customizable hardware IP cores for the Reinforcement Learning algorithm called Q-Learning. The tool automatically produces the VHDL code and runs both synthesis and implementation for any AMD-Xilinx FPGA using the Vivado software chain. Our automatic generator relies on the “HDL coder” from Mathworks to produce an efficient hardware accelerator based on the state of the art. The model can be customized by the user according to the desired Q-Matrix size and bit-depth for all the algorithm parameters.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
