This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.
Campitelli, S., Ottavi, M., Pontarelli, S., Marchioro, A., Felici, D., Lombardi, F. (2013). F-DICE: a multiple node upset tolerant flip-flop for highly radioactive environments. In 2013 IEEE International Symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT) (pp.107-111). IEEE [10.1109/DFT.2013.6653591].
F-DICE: a multiple node upset tolerant flip-flop for highly radioactive environments
OTTAVI, MARCO;PONTARELLI, SALVATORE;
2013-10-01
Abstract
This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.| File | Dimensione | Formato | |
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