Real-time cache management framework for multi-core architectures

Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to compute the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose a complete framework to (1) analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce a deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks.