Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to compute the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose a complete framework to (1) analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce a deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks.

Mancuso, R., Dudko, R., Betti, E., Cesati, M., Caccamo, M., Pellizzoni, R. (2013). Real-time cache management framework for multi-core architectures. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) (pp.45-54). Institute of Electrical and Electronics Engineers ( IEEE ) [10.1109/RTAS.2013.6531078].

Real-time cache management framework for multi-core architectures

CESATI, MARCO;
2013-01-01

Abstract

Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to compute the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose a complete framework to (1) analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce a deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks.
2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS 2013)
Philadelphia, Pennsylvania, USA
2013
19
IEEE
Rilevanza internazionale
contributo
9-apr-2013
2013
Settore ING-INF/05 - SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
English
Cache allocation; Cache management; Cache management techniques; Complete system; Hardware resources; Memory access patterns; Multicore architectures; Multicore chips
Best student paper award
https://ieeexplore.ieee.org/document/6531078
Intervento a convegno
Mancuso, R., Dudko, R., Betti, E., Cesati, M., Caccamo, M., Pellizzoni, R. (2013). Real-time cache management framework for multi-core architectures. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) (pp.45-54). Institute of Electrical and Electronics Engineers ( IEEE ) [10.1109/RTAS.2013.6531078].
Mancuso, R; Dudko, R; Betti, E; Cesati, M; Caccamo, M; Pellizzoni, R
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/81932
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