A simple synthesis methodology for 3-stage LNA design in GaAs technology

This work presents a new approach to design a three-stage LNA starting from the deterministic design of a two-stage LNA. The first two stages are composed of common-source stages with inductive source degeneration, while the third stage consists of an RC network attached prior to the common-source FET transistor. The LNA was implemented using WIN Foundry's PIH1-I0 Gallium Arsenide (GaAs) E-mode technology. The input matching networks are designed to satisfy the optimum noise measure termination, which leads to a noise figure of 1.62 dB. The measurements confirm that input and output matching are better than 13 dB at the central frequency, i.e., 15 GHz. The highest gain level of 25 dB is reported when operating at 13 G Hz. The slight deterioration between the measurements and EM simulations is ascribed to the discrepancy in precision between the software's models and the real models. Only the small signal measurements are reported in this work, the noise figure measurements are undergoing and will be available by the time of the conference.