This paper investigates the effects of a class of transient faults, the so-called Single Event Upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility.

Ottavi, M., Pontarelli, S., Leandri, A., Salsano, A. (2006). Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp.371-379). Los Alamitos : IEEE computer Soc [10.1109/DFT.2006.21].

Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers

OTTAVI, MARCO;PONTARELLI, SALVATORE;SALSANO, ADELIO
2006-01-01

Abstract

This paper investigates the effects of a class of transient faults, the so-called Single Event Upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility.
2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Arlington, VA
4 October 2006 through 6 October 2006
IEEE
Rilevanza internazionale
2006
Settore ING-INF/01 - ELETTRONICA
English
microcontrollers; fault injection; prograrn-flow checking; FPGA; partial reconfiguration
Intervento a convegno
Ottavi, M., Pontarelli, S., Leandri, A., Salsano, A. (2006). Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp.371-379). Los Alamitos : IEEE computer Soc [10.1109/DFT.2006.21].
Ottavi, M; Pontarelli, S; Leandri, A; Salsano, A
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/30187
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus ND
  • ???jsp.display-item.citation.isi??? ND
social impact