This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks.
Asciolla, D., Dilillo, L., Santos, D., Melo, D., Menicucci, A., Ottavi, M. (2020). Characterization of a RISC-V Microcontroller Through Fault Injection. ??????? it.cilea.surplus.oa.citation.tipologie.CitationProceedings.prensentedAt ??????? International Conference on Applications in Electronics Pervading Industry, Environment and Society, ApplePies 2019 [10.1007/978-3-030-37277-4_11].
Characterization of a RISC-V Microcontroller Through Fault Injection
Ottavi M.
2020-01-01
Abstract
This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
