At mm wave, and sub-THz frequencies the foundry usually does not provide information about the power amplifying capability or optimum impedances of the transistors for maximum power, and efficiency. Therefore, in this paper, we studied and analyzed the size of a SiGe HBT (Heterojunction Bipolar Transistor) in terms of output power and efficiency performance for the design of a power amplifier (PA) operating at 160 GHz. Load pull simulations were performed for various size of transistors. Optimum size transistors resulting in high power and efficiency are used to design a 160 GHz power amplifier using the foundry models for transmission lines and MIM capacitors. The simulated power amplifier (excluding interconnects for transistors and MIM) achieves a simulated output power of 18 dBm with a power added efficiency (PAE) of 19%. Future work includes the design of low loss interconnects for transistors and MIM capacitors, and fabrication of the power amplifier.
Ali, A., Cipriani, E., Johansen, T.k., Colantonio, P. (2018). Study of 130 nm SiGe HBT Periphery in the Design of 160 GHz Power Amplifier. In 2018 First International Workshop on Mobile Terahertz Systems (IWMTS) (pp.1-5). IEEE [10.1109/IWMTS.2018.8454697].
Study of 130 nm SiGe HBT Periphery in the Design of 160 GHz Power Amplifier
Cipriani, Elisa;Colantonio, Paolo
2018-01-01
Abstract
At mm wave, and sub-THz frequencies the foundry usually does not provide information about the power amplifying capability or optimum impedances of the transistors for maximum power, and efficiency. Therefore, in this paper, we studied and analyzed the size of a SiGe HBT (Heterojunction Bipolar Transistor) in terms of output power and efficiency performance for the design of a power amplifier (PA) operating at 160 GHz. Load pull simulations were performed for various size of transistors. Optimum size transistors resulting in high power and efficiency are used to design a 160 GHz power amplifier using the foundry models for transmission lines and MIM capacitors. The simulated power amplifier (excluding interconnects for transistors and MIM) achieves a simulated output power of 18 dBm with a power added efficiency (PAE) of 19%. Future work includes the design of low loss interconnects for transistors and MIM capacitors, and fabrication of the power amplifier.File | Dimensione | Formato | |
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