A Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Doherty Power Amplifier (DPA) for 7 GHz microwave backhaul radio links is presented. The MMIC is based on a novel design approach that allows for a drastic reduction of the phase distortion (AM/PM) without worsening other key features, such as efficiency and gain. In the proposed architecture, a nonlinear driver stage is introduced in both Carrier and Peaking branches, with the aim to actualize a phase distortion compensation mechanism directly at MMIC level, thus heavily mitigating the linearity issues at system level. In addition, the power consumption of the driver stages has been minimized by adopting an uneven drain bias voltage. The design has been carried out on a commercial 0.25 μm GaN power process, resulting in an overall chip area of 3×3mm2. The MMIC shows 38 dBm of saturated output power, 16 dB of gain, and less than 3° of phase distortion at 7 GHz. The power added efficiency is higher than 47% in 7 dB of output power back off.
Giofre', R., Colantonio, P., Giannini, F. (2016). A design approach to mitigate the phase distortion in GaN MMIC Doherty Power Amplifiers. In Microwave Integrated Circuits Conference (EuMIC), 2016 11th European (pp.133-136). IEEE [10.1109/EuMIC.2016.7777508].
A design approach to mitigate the phase distortion in GaN MMIC Doherty Power Amplifiers
GIOFRE', ROCCO;COLANTONIO, PAOLO;GIANNINI, FRANCO
2016-01-01
Abstract
A Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Doherty Power Amplifier (DPA) for 7 GHz microwave backhaul radio links is presented. The MMIC is based on a novel design approach that allows for a drastic reduction of the phase distortion (AM/PM) without worsening other key features, such as efficiency and gain. In the proposed architecture, a nonlinear driver stage is introduced in both Carrier and Peaking branches, with the aim to actualize a phase distortion compensation mechanism directly at MMIC level, thus heavily mitigating the linearity issues at system level. In addition, the power consumption of the driver stages has been minimized by adopting an uneven drain bias voltage. The design has been carried out on a commercial 0.25 μm GaN power process, resulting in an overall chip area of 3×3mm2. The MMIC shows 38 dBm of saturated output power, 16 dB of gain, and less than 3° of phase distortion at 7 GHz. The power added efficiency is higher than 47% in 7 dB of output power back off.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
