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EnglishThis paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.
Kan, S., Ottavi, M., & Dworak, J. (2015). Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on (pp.119-122). IEEE.
| Autori: | |
| Autori: | Kan, S; Ottavi, M; Dworak, J |
| Titolo: | Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation |
| Nome del convegno: | 28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 |
| Luogo del convegno: | University of Massachusetts, usa |
| Anno del convegno: | 2015 |
| Rilevanza: | Rilevanza internazionale |
| Data di pubblicazione: | 2015 |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/DFT.2015.7315147 |
| Settore Scientifico Disciplinare: | Settore ING-INF/01 - Elettronica |
| Lingua: | English |
| Tipologia: | Intervento a convegno |
| Citazione: | Kan, S., Ottavi, M., & Dworak, J. (2015). Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on (pp.119-122). IEEE. |
| Appare nelle tipologie: | 02 - Intervento a convegno |
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http://hdl.handle.net/2108/132009
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