This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.

Kan, S., Ottavi, M., Dworak, J. (2015). Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on (pp.119-122). IEEE [10.1109/DFT.2015.7315147].

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

OTTAVI, MARCO;
2015-01-01

Abstract

This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.
28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
University of Massachusetts, usa
2015
Rilevanza internazionale
2015
Settore ING-INF/01 - ELETTRONICA
English
Intervento a convegno
Kan, S., Ottavi, M., Dworak, J. (2015). Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on (pp.119-122). IEEE [10.1109/DFT.2015.7315147].
Kan, S; Ottavi, M; Dworak, J
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/132009
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