Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall).

Goel, B., Mckee, S., Gioiosa, R., Singh, K., Bhadauria, M., Cesati, M. (2010). Portable, scalable, per-core power estimation for intelligent resource management. In International conference on green computing - conference proceedings (pp.135-146). Red Hook, NY, USA : IEEE [10.1109/GREENCOMP.2010.5598313].

Portable, scalable, per-core power estimation for intelligent resource management

CESATI, MARCO
2010-10-07

Abstract

Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall).
2010 International conference on green computing
Chicago, IL
2010
IEEE
Rilevanza internazionale
contributo
15-ago-2010
7-ott-2010
Settore ING-INF/05 - Sistemi di Elaborazione delle Informazioni
English
power consumption; power-aware computing; multi-core computer
IEEE Catalog Number CFP1028K-PRT
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5598313
Intervento a convegno
Goel, B., Mckee, S., Gioiosa, R., Singh, K., Bhadauria, M., Cesati, M. (2010). Portable, scalable, per-core power estimation for intelligent resource management. In International conference on green computing - conference proceedings (pp.135-146). Red Hook, NY, USA : IEEE [10.1109/GREENCOMP.2010.5598313].
Goel, B; Mckee, S; Gioiosa, R; Singh, K; Bhadauria, M; Cesati, M
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/11824
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