The VLSI implementation of Cellular Neural Networks is a relevant task which is very important for the future development of neural networks. In this paper a a modular VLSI implementation of a 3×3 Digitally Programmable Cellular Neural Networks is presented. This chip is the first successfully tested fully programmable Cellular Neural Network hardware implementation. It covers most of the available one-neighborhood templates for image processing applications. Moreover, it has been designed to be easily interconnected to others to give very large CNN arrays
Salerno, M., Sargeni, F., Bonaiuto, V. (1995). DPCNN: a modular chip for large CNN arrays. In IEEE International Symposium on Circuits and Systems, 1995. ISCAS '95. (pp.417-420) [10.1109/ISCAS.1995.521539].
DPCNN: a modular chip for large CNN arrays
SALERNO, MARIO;SARGENI, FAUSTO;BONAIUTO, VINCENZO
1995-01-01
Abstract
The VLSI implementation of Cellular Neural Networks is a relevant task which is very important for the future development of neural networks. In this paper a a modular VLSI implementation of a 3×3 Digitally Programmable Cellular Neural Networks is presented. This chip is the first successfully tested fully programmable Cellular Neural Network hardware implementation. It covers most of the available one-neighborhood templates for image processing applications. Moreover, it has been designed to be easily interconnected to others to give very large CNN arraysI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
