The design and realisation of reliable hardware CNN systems with a high number of cells is a key point in research in this field. On this topic, several different solutions have been proposed in VLSI implementations. In previously published papers, the authors presented current-mode interconnection-oriented integrated circuits to realise wide CNN networks. The multi-chip architecture shows the drawback to be a pad-limited structure because of the growing number of the pads required by the interconnections. In this paper a technique to improve the interconnection architecture without any lack of functionality will be presented. This approach will drastically cut the interconnection requirements by 75%. Some simulation results are presented together with experimental results
Sargeni, F., Salerno, M., & Bonaiuto, V. (1998). An improved Architecture for the interconnections in a multi-chip CNN system. In Proc of EEE International Conference on Circuits and Systems (ISCAS 98) (pp.143-146).
Autori: | |
Autori: | Sargeni, F; Salerno, M; Bonaiuto, V |
Titolo: | An improved Architecture for the interconnections in a multi-chip CNN system |
Nome del convegno: | IEEE International Symposium on Circuits and Systems,(ISCAS 98) |
Luogo del convegno: | Monterey, CA - USA |
Anno del convegno: | 1998 |
Rilevanza: | Rilevanza internazionale |
Data di pubblicazione: | 1998 |
Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/ISCAS.1998.703930 |
Settore Scientifico Disciplinare: | Settore ING-IND/31 - Elettrotecnica |
Lingua: | English |
Tipologia: | Intervento a convegno |
Citazione: | Sargeni, F., Salerno, M., & Bonaiuto, V. (1998). An improved Architecture for the interconnections in a multi-chip CNN system. In Proc of EEE International Conference on Circuits and Systems (ISCAS 98) (pp.143-146). |
Appare nelle tipologie: | 02 - Intervento a convegno |