Design and analysis of single event tolerant slave latches for enhanced scan delay testing

The last few years have seen the development and fabrication of nanoscale circuits at high density and low power. Following a single-event upset (SEU), so-called soft errors due to internal and externally induced phenomena (such as α-particles and cosmic rays in adverse environments) have been reported during system operation; this is especially deleterious for storage elements such as flip-flops. To reduce the impact of a soft error on flip-flops, hardening techniques have been utilized. This paper proposes two new slave latches for improving the SEU tolerance of a flip-flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. When used in a flip-flop, the first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16% (9%) power consumption overhead at 32-nm feature size, as compared with the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple-node upset.