Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency
Quaglia, R., Pirola, M., Ghione, G., Ciccognani, W., Limiti, E. (2014). 13-bit GaAs serial to parallel converter with compact layout for core-chip applications. MICROELECTRONICS JOURNAL, 45(7), 864-869 [10.1016/j.mejo.2014.04.036].
13-bit GaAs serial to parallel converter with compact layout for core-chip applications
CICCOGNANI, WALTER;LIMITI, ERNESTO
2014-07-01
Abstract
Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequencyFile in questo prodotto:
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