Approximate Computing has emerged as a viable solution to resource constraints in computing for error-resilient applications by relaxing accuracy for significant gains in terms of power, performance, and area. Among existing approximation techniques, the self-healing methodologies have shown a promising quality-efficiency balance by canceling out the overall effect of computational errors. However, they rely on highly parallel implementations for error cancellation. In our prior work (MACISH), we proposed an Internal-Self-Healing (ISH) methodology that applies approximations in the recursive multiplication stage and leverages the accumulation stage for error cancellation, eliminating the need for paired parallel modules required by traditional self-healing approaches. ASIC-based digital designs proposed by MACISH demonstrated superior quality-efficiency results for the radio astronomy application. However, the architectural differences limit the direct mapping of ASIC-based optimized designs to FPGAs. Therefore, this article addresses the gap by designing the FPGA-based Pareto-optimal 4-bit and 8-bit recursive approximate multipliers using ISH methodology. The proposed Design Space Exploration (DSE) strategy manages the vast 8-bit design space by deriving the candidate designs from 4-bit Pareto-optimal multipliers, reducing the search complexity while preserving the performance. The proposed designs achieve up to 12% and 33.6% better power and energy efficiency, respectively, compared to accurate 8-bit multipliers and up to 30× improved output quality at a similar area. The design flow is automated using the 'Approxy' Tool, which has also been developed as part of this work. For the radio astronomy correlation application, these designs achieved comparable (and acceptable) output quality with respect to the state-of-the-art. For Deep Learning (DL) workloads, the proposed 8-bit designs matched or even exceeded the baseline accuracy for binary and multiclass classification problems.

Rasheed, Y., Van Der Wijk, R.h., Van Loo, R., Jauregui Morris, R.a., Gillani, G.a., Kokkeler, A., et al. (2026). AMPEREISH: Approximate Multipliers for Power Efficiency in FPGA Designs Using Internal-Self-Healing. IEEE ACCESS, 14, 60252-60267 [10.1109/ACCESS.2026.3684720].

AMPEREISH: Approximate Multipliers for Power Efficiency in FPGA Designs Using Internal-Self-Healing

Ottavi, Marco
2026-01-01

Abstract

Approximate Computing has emerged as a viable solution to resource constraints in computing for error-resilient applications by relaxing accuracy for significant gains in terms of power, performance, and area. Among existing approximation techniques, the self-healing methodologies have shown a promising quality-efficiency balance by canceling out the overall effect of computational errors. However, they rely on highly parallel implementations for error cancellation. In our prior work (MACISH), we proposed an Internal-Self-Healing (ISH) methodology that applies approximations in the recursive multiplication stage and leverages the accumulation stage for error cancellation, eliminating the need for paired parallel modules required by traditional self-healing approaches. ASIC-based digital designs proposed by MACISH demonstrated superior quality-efficiency results for the radio astronomy application. However, the architectural differences limit the direct mapping of ASIC-based optimized designs to FPGAs. Therefore, this article addresses the gap by designing the FPGA-based Pareto-optimal 4-bit and 8-bit recursive approximate multipliers using ISH methodology. The proposed Design Space Exploration (DSE) strategy manages the vast 8-bit design space by deriving the candidate designs from 4-bit Pareto-optimal multipliers, reducing the search complexity while preserving the performance. The proposed designs achieve up to 12% and 33.6% better power and energy efficiency, respectively, compared to accurate 8-bit multipliers and up to 30× improved output quality at a similar area. The design flow is automated using the 'Approxy' Tool, which has also been developed as part of this work. For the radio astronomy correlation application, these designs achieved comparable (and acceptable) output quality with respect to the state-of-the-art. For Deep Learning (DL) workloads, the proposed 8-bit designs matched or even exceeded the baseline accuracy for binary and multiclass classification problems.
2026
Pubblicato
Rilevanza internazionale
Articolo
Esperti anonimi
Settore IINF-01/A - Elettronica
English
Approximate computing; Approximate multiplier; Deep learning; FPGA; Internal self-healing; Radio astronomy; Recursive multiplier
Rasheed, Y., Van Der Wijk, R.h., Van Loo, R., Jauregui Morris, R.a., Gillani, G.a., Kokkeler, A., et al. (2026). AMPEREISH: Approximate Multipliers for Power Efficiency in FPGA Designs Using Internal-Self-Healing. IEEE ACCESS, 14, 60252-60267 [10.1109/ACCESS.2026.3684720].
Rasheed, Y; Van Der Wijk, Rh; Van Loo, R; Jauregui Morris, Ra; Gillani, Ga; Kokkeler, Abj; Ottavi, M
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/463823
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