Design of hardware architectures for the acceleration of machine learning algorithms

This Doctoral dissertation is the result of a three-year research, from 2018 to 2021, in the field of hardware acceleration of Machine Learning algorithms. Whether Supervised, Unsupervised, and Reinforcement Learning methods have been addressed, covering all the possible Machine Learning categories. The thesis includes the most relevant candidate’s papers which have been published in high-profile scientific journals or presented at influential international symposiums. Different hardware architectures and implementations are proposed, such as the Pseudo-Softmax layer for Artificial Neural Networks, a Hierarchical Clustering technique based on fuzzy logic, and a Q-Learning hardware accelerator. Among the contributions of this work are All Winner - Self-Organizing Maps (AW-SOM) and Q-learning Real Time Swarm (Q-RTS), two novel Unsupervised and Reinforcement Learning algorithms suitable for efficient hardware implementations in terms of processing speed, power dissipation, and required hardware resources.