Insight into optimally noise- and signal-matched three-stage LNAs and effect of inter-stage mismatch

This manuscript provides insight into optimally noise-matched three-stage Low-Noise Amplifiers (LNAs) by proposing a novel chart that illustrates the relationship between the gain of a three-stage LNA and inter-stage mismatch levels. Under certain conditions, the chart also indicates the required feedback inductor values for all transistors. It is demonstrated that, under the specific assumption of optimal noise and signal matching, the LNA gain depends on the levels of two inter-stage mismatches. Contrary to common belief, the results show that the LNA gain increases as the inter-stage mismatch levels rise. This finding is supported through the discussion of two LNA designs, one with lower and one with higher inter-stage mismatch levels, achieving gains of 24 dB and 26 dB, respectively, with a Noise Figure of 1.7 dB at the center design frequency of 28 GHz. Subsequently, one LNA topology is validated in a Monolithic Microwave Integrated Circuit (MMIC) implementation using WIN Foundry's PIH1-10 GaAs E-mode technology. The MMIC characterization aligns with the simulated behavior, accounting for the unavoidable losses in the matching networks.