Partially reversible pipelined QCA circuits: combining low power with high throughput

This paper introduces an architecture for quantum- dot cellular automata circuits with the potential for high through- put and low power dissipation. The combination of regions with Bennett clocking and memory storage combines the low power advantage of reversible computing with the high throughput ad- vantage of pipelining. Two case studies are initially presented to evaluate the proposed pipelined architecture in terms of through- put and power consumption due to information dissipation. A general model for assessing power consumption is also proposed. This paper shows that the advantages possible by using a Bennett clock- ing scheme also depend on circuit topology, thus also confirming the validity of the proposed analysis and model.