Novel memory circuits based on variable-resistance devices (such as memristors) have been recently proposed to over- come the limitations of CMOS based memories. These novel memo- ries although based on different technologies, all share the principle of storing information as the resistance value imposed to a variable- resistance devices. Another promising application of memristors is in content-addressable memory (CAM). The study of memristor based CAM design has become increasingly important with the advent of new hybrid CMOS molecular technologies. To this end, we present a two-transistor–memristor (2T2M) bitcell for CAM design, suitable for low-power applications. The proposed circuit consists of memristors to store data and transistors as access de- vices, and utilizes complementary logic values at the input. We present detailed simulation based characterization (for both full match and partial match cases) and analysis, considering different word sizes of the proposed bitcells, including full parasitics, using BPTM 45-nm CMOS device models.
Yang, Y., Mathew, J., Chakraborty, R., Ottavi, M., Pradhan, D. (2016). Low cost memristor associative memory design for full and partial matching applications. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 15(3), 527-538 [10.1109/TNANO.2016.2553438].
Low cost memristor associative memory design for full and partial matching applications
OTTAVI, MARCO;
2016-01-01
Abstract
Novel memory circuits based on variable-resistance devices (such as memristors) have been recently proposed to over- come the limitations of CMOS based memories. These novel memo- ries although based on different technologies, all share the principle of storing information as the resistance value imposed to a variable- resistance devices. Another promising application of memristors is in content-addressable memory (CAM). The study of memristor based CAM design has become increasingly important with the advent of new hybrid CMOS molecular technologies. To this end, we present a two-transistor–memristor (2T2M) bitcell for CAM design, suitable for low-power applications. The proposed circuit consists of memristors to store data and transistors as access de- vices, and utilizes complementary logic values at the input. We present detailed simulation based characterization (for both full match and partial match cases) and analysis, considering different word sizes of the proposed bitcells, including full parasitics, using BPTM 45-nm CMOS device models.File | Dimensione | Formato | |
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