We propose a NMOS low drop-out voltage regulator suitable for on-chip power management. The circuit does not requires any external components for achieving compensation since it is internally compensated. A dynamic biasing strategy and a clock booster allows to properly drive the NMOS power transistor in a power efficient fashion and without limiting the speed response of the regulator. Transistor level simulations confirm the effectiveness of the proposed approach. © 2008 Springer Science+Business Media, LLC.
Giustolisi, G., Falconi, C., D'Amico, A., Palumbo, G. (2009). On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 58(2), 81-90 [10.1007/s10470-008-9234-1].
On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique
FALCONI, CHRISTIAN;D'AMICO, ARNALDO;
2009-01-01
Abstract
We propose a NMOS low drop-out voltage regulator suitable for on-chip power management. The circuit does not requires any external components for achieving compensation since it is internally compensated. A dynamic biasing strategy and a clock booster allows to properly drive the NMOS power transistor in a power efficient fashion and without limiting the speed response of the regulator. Transistor level simulations confirm the effectiveness of the proposed approach. © 2008 Springer Science+Business Media, LLC.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
