Accelerators such as NVIDIA GPUs and Intel MICs are currently provided as co-processor devices, usable only through a CPU host. For Intel MICs it is planned that this constraint will be lifted in the near future: CPU and accelerator(s) will then form a single, many-core, processor capable of peak performance of several Teraflops with high energy efficiency. In order to exploit the available computational power, the user will be compelled to write a code more “hardware-aware”, in contrast to the common philosophy of hiding hardware details as much as possible. The simple two-sided communication approach often used in message-passing applications introduces synchronization costs that may limit the performance on the next generation machines. PGAS languages, like coarray Fortran and UPC, propose a one-sided approach where a process accesses directly the remote memory of another process without interrupting its execution. In this paper, we propose a CUDA-aware coarray implementation, capable of merging the expressive syntax of coarrays with the computational power of GPUs. We propose a new keyword for the Fortran language, which allows the user to map with a high-level syntax some hardware features of the many-core machines. Our hybrid coarray implementation is based on OpenCoarrays, the coarray transport layer currently adopted by the GNU Fortran compiler.

Cardellini, V., Fanfarillo, A., Filippone, S., Rouson, D. (2016). Hybrid coarrays: A PGAS feature for many-core architectures. In Parallel Computing: On the Road to Exascale (pp.175-184). Amsterdam : IOS Press [10.3233/978-1-61499-621-7-175].

Hybrid coarrays: A PGAS feature for many-core architectures

CARDELLINI, VALERIA;FILIPPONE, SALVATORE;
2016-01-01

Abstract

Accelerators such as NVIDIA GPUs and Intel MICs are currently provided as co-processor devices, usable only through a CPU host. For Intel MICs it is planned that this constraint will be lifted in the near future: CPU and accelerator(s) will then form a single, many-core, processor capable of peak performance of several Teraflops with high energy efficiency. In order to exploit the available computational power, the user will be compelled to write a code more “hardware-aware”, in contrast to the common philosophy of hiding hardware details as much as possible. The simple two-sided communication approach often used in message-passing applications introduces synchronization costs that may limit the performance on the next generation machines. PGAS languages, like coarray Fortran and UPC, propose a one-sided approach where a process accesses directly the remote memory of another process without interrupting its execution. In this paper, we propose a CUDA-aware coarray implementation, capable of merging the expressive syntax of coarrays with the computational power of GPUs. We propose a new keyword for the Fortran language, which allows the user to map with a high-level syntax some hardware features of the many-core machines. Our hybrid coarray implementation is based on OpenCoarrays, the coarray transport layer currently adopted by the GNU Fortran compiler.
International Conference on Parallel Computing (ParCo 2015)
Edinburgh, UK
2015
Rilevanza internazionale
contributo
set-2015
2016
Settore ING-INF/05 - SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
English
Accelerators; Coarrays; CUDA; Fortran; PGAS;
http://ebooks.iospress.nl/publication/42655
Intervento a convegno
Cardellini, V., Fanfarillo, A., Filippone, S., Rouson, D. (2016). Hybrid coarrays: A PGAS feature for many-core architectures. In Parallel Computing: On the Road to Exascale (pp.175-184). Amsterdam : IOS Press [10.3233/978-1-61499-621-7-175].
Cardellini, V; Fanfarillo, A; Filippone, S; Rouson, D
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2108/148547
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