3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz

This article presents the design strategy and the implementation of a three-way Doherty power amplifier (DPA3W) to enhance the efficiency at deep power back-off. Theoretical design equations are derived, based on which design charts are drawn to explore the available design space, accounting for practical constraints related to the available technology and selected application. The proposed design strategy is demonstrated by the design, fabrication and experimental characterization of a three-way multistage Doherty amplifier optimized for efficiency peaks at 6 and 12 dB back-off. The amplifier is realized on the WIN Semiconductors 150 nm GaN-SiC high-electron-mobility transistor (HEMT) monolithic process at 28 GHz, targeting 5G applications. The prototype achieves saturated output power in excess of 34 dBm and power added efficiency of the order of 15% from 6 to 12 dB back-off, demonstrating competitive performance and a good agreement between simulations and measurements, thus validating the approach.


I. INTRODUCTION
T HE demand for high capacity of future communication systems forces the adoption of advanced modulation schemes with non-constant envelope and very large peakto-average-power-ratio (PAPR). This has a strong impact on the transmitter architecture, especially on the power amplifier (PA), which operates in back-off, i.e., at an average power significantly lower than its saturated one.
At sub-6 GHz communication frequencies, different design strategies have been proposed to maintain also in back-off a reasonably high PA efficiency, the most popular one being presently the Doherty PA (DPA) [1], [2], [3], thanks to its relatively simple and robust design, and its good performance in terms of efficiency and linearity over bandwidths compatible with today's standard requirements. Different metrics are currently in use to specify the linearity requirements of the PAs, Manuscript  noise-to-power ratio (NPR) [4] becoming increasingly popular for satellite communications, whereas adjacent channel power ratio (ACPR) and error vector magnitude (EVM) being among the most used for ground communications. However, 5G applications and beyond would soon require the PA to manage signals with increasing PAPR (9-12 dB), well beyond the classical 6-dB high-efficiency region of standard DPAs. Crest Factor Reduction can be applied, although at the expense of increased complexity and worse linearity [5]. Therefore, architectures to enhance the efficiency at deep power back-off, such as the N-stage and N-way DPA [6], [7], [8], [9], [10], [11], the distributed efficient PA (DEPA) [12], [13], and the sequential-load modulated balanced amplifier (S-LMBA) [14], [15], [16], [17], have been developed.
The DPA and S-LMBA architectures typically rely on a limited number of active devices (usually three, one for the Main and two for the Auxiliary), but they are particularly affected by a strong gain penalty, due to the asymmetric input power splitting and the class-C bias point adopted for the Auxiliary devices [6], [9], [17]. Optimized operations in terms of achievable gain and efficiency are possible but require multi-RF-inputs [7], [10]. On the other side, the DEPA has a somewhat limited gain penalty but needs an increasingly high number of active devices to optimize the efficiency at a deeper output power back-off (OBO) [12], [13]. In addition, the DEPA and S-LMBA eliminate the load modulation of the Main, thus favoring wideband operation, but at the cost of overdriving it over the whole high-efficiency region, with unavoidable reliability and stress issues. The Main overdriving issue is also present in some of the N-stage and N-way DPAs proposed in literature [6], [7], [9], being based on output combiners that hamper the modulation of the Main load when more than one auxiliary stage is on. A viable solution for this limiting factor has been proposed in [18] and [19] and implemented at 2.65 GHz in [8]. In the latter, the novel output combiner scheme was exploited in conjunction with gate envelope tracking to mitigate the low load modulation due to the deep class-C bias of the auxiliary stages.
In general, most of the above-mentioned solutions are currently limited to single-stage hybrid demonstrators, with excellent efficiency but a limited gain (typically around 10 dB), and often complex architectures, limiting so far their adoption at higher communications frequencies, where PA architectures with one or more driver stages are inevitably called for. Recently, 6 dB DPAs and LMBAs are starting to appear at K a-band and 5G FR2 frequencies with competitive performance [20], [21], [22], [23], despite the need of multistage architectures. Therefore, this work aims at exploring the feasibility of deep-OBO DPAs at similar frequencies and their convenience as compared to more classical solutions with a less severe gain penalty.
Concerning these DPAs, the nomenclature is not unique; in this work, N-stage indicates N − 1 drivers and a final power stage, whereas M-way refers to a DPA with M efficiency peaks, and hence with M − 1 auxiliary devices.
In the following, a step-by-step design strategy for three-way DPAs (DPA3W) based on the combiner of [18] and [19] is provided. The complete design flow for the computation of the combiner's parameters as well as the devices' selection is presented, critically discussing the possible trade-offs and introducing general design charts to visualize the available design space when accounting for several technology constraints.
The approach is validated by the design and experimental characterization of a demonstrator targeting the FR2 5G band n261 , optimized at 6 and 12 dB OBO. The prototype, manufactured in the 150 nm GaN-SiC highelectron-mobility transistor (HEMT) process of WIN Semiconductors is, to the best of the authors' knowledge, the first monolithic microwave integrated circuit (MMIC) DPA3W. It compares well with the present state of the art at similar frequencies, demonstrating the validity of the approach and opening to the adoption of this strategy also for mm-wave applications.
This article is structured as follows. Section II reports the theoretical foundations and derives the design equations for a generic DPA3W, exploring the design space and the available degrees of freedom with the aid of graphical charts. In Section III, the theoretical formulation is applied to the design of an MMIC three-stage DPA3W demonstrator in GaN technology at 28 GHz. The experimental characterization results of the manufactured MMIC are presented in Section IV. Finally, conclusions are drawn in Section V.

II. THEORETICAL ANALYSIS
The proposed DPA3W architecture of Fig. 1(a) can synthesize the efficiency profile shown in Fig. 1(b) provided that the active devices are driven to generate current profiles like those of Fig. 1(c) and corresponding voltage response similar to those of Fig. 1(d). The two back-off efficiency peaks occur at a distance (in dB) OBO 2 and OBO from saturation. Assuming the simplified ideal behavior of the active devices, the following operating regions can be identified, relative to the normalized dynamic range (i.e., the driving input voltage)  2) x 1 ≤ x < x 2 (OBO 1 Region): At the first break point x = x 1 , M achieves its maximum voltage swing (voltage saturation) and A 1 turns on, modulating Z M , while A 2 is still off. The current provided by A 1 increases the impedance Z x , and the λ/4 TL Z 1 acts as an impedance inverting network, thus decreasing the value of Z M . 3) x 2 ≤ x ≤ 1 (OBO 2 Region): At the second break point x = x 2 , A 1 reaches its maximum voltage swing (voltage saturation), and A 2 turns on, modulating both Z M and Z A 1 . Indeed, the current injected by A 2 increases the impedance Z y , and the λ/4 TL Z 3 acts as an impedance inverting network for A 1 , thus decreasing the value of Z A 1 . Simultaneously, the currents of A 1 and A 2 further increase Z x , thus decreasing the impedance Z M . At x = 1 all devices are in saturation, i.e., operate with maximum current and voltage swings. At the input of the DPA3W, an ad hoc splitter is clearly required to properly compensate the phase shifts introduced by the λ/4 TLs of the output combiner, as well as appropriately dividing the input power among the three amplifying branches, thus leading to the final architecture reported in Fig. 1(a).
The fundamental components of the drain current and voltage of each device are indicated as I sub (x) and V sub (x), respectively, where sub corresponds to M, A 1 and A 2 for the Main, and the two Auxiliary devices, respectively.
The maximum voltage (peak value) for each device is where the supply (V DD,sub ) and knee (V k,sub ) voltages can in general be different among the stages. Therefore, it is useful to define the normalization coefficient Similarly, the maximum current (peak value) of each device will be indicated in the following as I Max,sub . Its relation with the fundamental current component at saturation [I sub (1)] depends on the bias point of the device, i.e., its quiescent current I DQ,sub . By defining the normalized quiescent current ξ sub = I DQ,sub /I Max,sub , the relation with the peak fundamental current is where I 1 (ξ, x) is the coefficient of the fundamental component of a truncated (normalized) sinusoidal waveform given by [18], [24] , otherwise.
Since all circuit elements are assumed to be lossless, the output power of the DPA3W is given by the sum of the output powers of the three devices where The design relationships for the proposed DPA3W are derived by assuming as design goals the position of the efficiency peaks (x 1 and x 2 ) and the target output power at saturation [P DPA,sat = P DPA (1)], and as free parameters the common-node resistance R L and the bias point of the Main, expressed in terms of drain voltage V DD,M and quiescent current I DQ,M . The characteristic impedances of the λ/4 TLs of the output combiner (Z 1 , Z 2 , Z 3 ), the bias points of A 1 and A 2 , and the maximum currents of all devices (I Max,M , I Max,A 1 , I Max,A 2 ) are derived accordingly. Note that in the following the 90 • phase rotation in any relation across a λ/4 TL is omitted since all quantities represent the magnitude of the corresponding phasors. In other words, it is assumed that the phase of the branch signals is such as to ensure in-phase current summation at the common node (i.e., into R L ).

A. Derivation of the Combiner's Parameters
With reference to Fig. 1(a) and accounting for the constitutive equation of a λ/4 TL at center frequency [25], it follows that I x is constant for x 1 ≤ x ≤ 1. Thus, the following relevant parameters can be derived: which, accounting for the generic definition of OBO = − 10 log 10 P DPA (x)/P DPA (1), are also given by where OBO and OBO 2 are design goals. By combining (8) and (9), one finds a relation between the overall current coming from the Auxiliary branches (I z ) and the one of the Main (I x ), at x 2 and saturation Adopting (8) and (12), I x (1) can be expressed as function of R L and P DPA,sat Since M achieves voltage saturation at The characteristic impedance of the λ/4 TL in front of M can be derived from (13) Similarly, the characteristic impedance of the λ/4 TL in front of A 2 can be derived by using (12) and (13) whereas, considering that and by using (11), (13), and (15), the characteristic impedance of the λ/4 TL in front of A 1 results Notably, (14), (15), and (17) allow the synthesis of the output combiner once the values of OBO, OBO 2 , and P DPA,sat are chosen.

B. Derivation of the Active Devices' Parameters
To complete the synthesis of the output section of the DPA3W, it is necessary to estimate the maximum current required by each device, and thus their active periphery. This can be accomplished deriving first their fundamental component at saturation I sub (1) and then the associated maximum current I Max,sub by using (3)-(5). Exploiting the λ/4 TL properties, Kirchoff current law (KCL) at x = 1, and (14)-(6), one finds It is worth noting that the fundamental current components do not depend on R L , confirming that the latter can be used as a free parameter to widen the design space, i.e., increase the feasibility of the characteristic impedances of the λ/4 TLs given by (14)- (17), in the selected technology.
Assuming the bias condition of M as a free parameter, its I Max,M can be derived by substituting (18) in (3) and exploiting (4) and (5) The maximum current of the Auxiliary devices can be derived by combining (19), (20), (18), and (3)-(5) To ensure the proper turn-on of the Auxiliary devices, it is possible to compute their virtual negative bias point ξ A n as being the breakpoints x n the solutions of the following equation [24]: which defines the linear current profile of the Main device. Finally, the impedance at the current generator plane of each device is Z d i ,sub = V sub /I sub [which coincides with Z sub in Fig. 1(a)], whereas their optimum load resistance is given by A summary of the design procedure is provided in the flowchart of Fig. 2. It is worth mentioning that the combiner topology and the corresponding system of equations reported above can be easily extended to the case of DPAs with more than two efficiency peaks, i.e., more than two Auxiliary devices.

C. Feasibility Analysis and Design Space
The design procedure laid out up to now and summarized in Fig. 2 has no theoretical limitations and could be applied to synthesize, on paper, any M-way Doherty architecture having an arbitrary position of the efficiency peaks, saturated output power, operating frequency, etc. However, as usual, theory has to meet technology constraints to produce feasible designs. Considering MMIC technologies, once the DPA3W design goals are fixed, the main limitations associated with passive and active components are the feasibility of the characteristic impedances of the λ/4 TLs (Z 1 , Z 2 , and Z 3 ) and the maximum allowable current and voltage swings. Characteristic impedances can be considered feasible if included in the range 20-100 , almost independently of the specific technology. The maximum current and voltage swings, instead, are heavily affected by the semiconductor proprieties of the specific technologies. This leads to the identification of the active devices macro parameters such as current density, drain bias, knee, and breakdown voltages. Focusing on GaN technology for mm-wave applications (i.e., with a gate length of the order of 0.1-0.15 μm), the current density typically ranges within 400-1000 mA/mm, whereas recommended drain bias voltages are within 10-30 V. Both features, together with the corresponding knee voltage value, concur to determine the achievable output power from a chosen device.
Accounting for these considerations, design charts are provided in Fig. 3 to aid the designer to visualize the contrasting constraints that influence the DPA3W design space. In particular, the contours of Z i as functions of P DPA,sat and R L are reported, fixing the design goals to OBO = 12 dB and OBO 2 = 6 dB. Moreover, despite the developed theory allows to account for different drain bias voltage of the devices, in these charts only the cases with Fig. 3 The available space for each parameter is highlighted in the corresponding plots with shaded areas, whose intersection represents the overall design space, considering the output power as design goal. In the first case, i.e., V Max,M,A 1 ,A 2 = 16 for R L = 50 , the resulting Z 1 , would be practically unfeasible for any value of P DPA,sat ≤ 10 W. On the contrary, Z 2 is always feasible and does not pose any constraint, whereas Z 3 only depends on P DPA,sat and becomes feasible for relatively high power values, above 3 W. Anyway, if a P DPA,sat ≤ 10 W is required, the designer can select a lower value for the free parameter R L to accommodate such a need, at the expense of an additional post-matching network (PMN) (which inevitably impacts on area, losses, complexity). For instance, an output power of about 5 W can be achieved by setting R L = 20 which leads to more practical and feasible values of the output combiner impedances. However, Fig. 3(a)-(c) also show that P DPA,sat 4 W is not achievable with V Max,M,A 1 ,A 2 = 16 V due to the limitation on Z 3 . To design a DPA3W with OBO = 12 dB and OBO 2 = 6 dB and targeting relatively low output power, the designer has to play with the voltage swing across the devices in order to land on a feasible output combiner. For instance, Fig. 3 Notably, all the impedances become feasible and well inside the practical limits of 20-100 for any P DPA,sat ≤ 4 W, confirming both versatility and feasibility of the proposed architecture.

III. DESIGN
In this work, the 150 nm gate length GaN-SiC HEMT process by WIN Semiconductors is adopted to design a 3 W DPA3W for 5G applications around 28 GHz, optimized at 6 and 12 dB OBO. The normalized fundamental current, voltage, and impedance profiles for such an architecture assuming Fig. 4. Notably, the maximum current of the Auxiliary devices is 1.5 times higher than that of the Main. Therefore, either the Auxiliary devices will have a larger periphery, or the Main device will be under-utilized if three identical devices were to be used.

A. DPA3W Assessment in the Selected Technology
The selected technology has operating voltage V DD = 20 V, current density around 400-500 mA/mm, and a scalable non-linear model for the active devices. The knee voltage is estimated to be V k = 4 V, leading to V Max,sub ≤ 16 V. Despite the developed theory allows to account for the different bias conditions of the devices, the combiner design is here carried out based on a class-B approximation for all the devices, which can be considered sufficiently accurate. Therefore, (4) reduces to I 1 (x) = x, which implies I Max,sub = 2· I sub (1). Following the flowchart of Fig. 2, the design charts of Fig. 3(a)-(c), and the considerations made on the technology constraints, R L is set to =11.3 , which represents a reasonable trade-off between feasibility and complexity of the combiner. The parameters computed according to (14)- (17), and the corresponding maximum currents given by (21) and (22) A shunt L c,sub compensation of the reactance is possible, but it brings about a change of the resistance, i.e., a scaling of currents and voltages, from the combiner plane (C) to the intrinsic drain plane (D i ) highlighted in Fig. 5. Therefore, a recomputation of the combiner parameters is required. A more complex compensation strategy that does not modify the impedance levels is in theory possible, but it is avoided here due to the complexity and losses at this frequency. The values of the output parasitics and corresponding compensation elements are Max,A1/A2 = 12.6 V at plane C, due to the different parasitic and compensation networks. Therefore, the recomputed combiner parameters and maximum currents become Indeed, comparing the initial set of parameters with the final one, one can easily note that the characteristic impedances become more suitable for an MMIC implementation while the current values vary only slightly, and are still achievable with the formerly selected devices, i.e., the 4 × 75 μm for the Main and the 6 × 100 μm for each of the Auxiliary devices.
The optimum loads of the devices, computed according to (25) at plane D i , are R opt,M = 145 and R opt,A 1 = R opt,A 2 = 97 .

B. Output Combiner Implementation
The output combiner is implemented in lumped form, replacing each λ/4 TL section with its π C LC equivalent network derived at f 0 = 28 GHz [see Fig. 6(a)]. The resulting C and L, derived according to C Zi = 1/(2π f 0 Z i ) and L Zi = Z i /(2π f 0 ), are given in Table I. This implementation, together with the choice of compensating the device parasitics by means of a simple shunt inductive element, allows to minimize the number of circuit components, thus also complexity and losses. In fact, as shown in Fig. 6(a) and (b), the elements connected to the same node (highlighted in the same color) are merged into one equivalent reactive element, which results inductive on the M and A1 branches (L e,M , L e,A1 ), and capacitive on the A2 branch (C e,A2 ).
The real-to-real PMN from R L = 11.3 to 50 is implemented by means of two λ/4 TL sections, also implemented in lumped form. The resulting schematic of the DPA3W output section, translated into real circuit elements available in the selected MMIC process (where inductors are replaced by TLs due to layout as well as current handling issues) and optimized around 28 GHz, is shown in Fig. 7, where the output equivalent model of the transistors has been replaced by the full symbol (in blue). The optimization goals impose a trade-off between correct load modulation [as identified in Fig. 4 (right)] and limited losses (within −1.5 dB) across the whole dynamic range (i.e., at x = x 1 , x 2 , n1). Note that, in the synthesized architecture, the position of A 1 and A 2 is swapped for layout convenience. Also, the shunt capacitor C e,A2 has resulted unnecessary during the optimization and has therefore been removed. The simulated load modulation and losses, adopting as device model ideal current sources with LC parasitics, are shown in Fig. 8. According to Fig. 8(a)-(c), all the devices maintain the correct load modulation, nearly on the real axis at f 0 , and reasonably close to it from 27.5 to 28.5 GHz. The power losses (both mismatch and ohmic) are maintained within the targeted range across the whole high-efficiency region, and are lower at saturation than at the back-off points.

C. Two-Stage DPA3W Architecture
Simulated power sweeps of the 4 × 75 μm and 6 × 100 μm devices at 28 GHz return power gain and peak efficiency around 10 dB and 55%, respectively, for a class-AB bias (100 mA/mm) on the optimum load.
Given the input power splitting factors required to synthesize the current profiles of Fig. 4 with the selected devices, a single-stage DPA3W architecture results unfeasible. The insertion of a driver in each of the branches is needed to ensure sufficient gain. Drivers able to correctly drive the corresponding final stage are, respectively, the 2 × 100 μm for the Main and 4 × 75 μm for the Auxiliary stages.  All devices are stabilized in and out of the band by means of a series R stab,1 C stab network and a shunt R stab,2 -L stab (which will be implemented as an inductive stub), whose values are reported in Table II. The interstage (IS) and input (I) matching networks (MNs) are designed to minimize reflections, thus maximizing the power transfer along the transistor chain. The ISMNs transform the input impedance of the stabilized power devices into the optimum load of the drivers, whereas the IMNs transform  TABLE III   CIRCUIT PARAMETERS OF THE ISMNS AND IMNS   TABLE IV CIRCUIT PARAMETERS OF THE INPUT SPLITTER the input impedance of the stabilized driver devices into 50 . In both cases, a similar low-order filter topology (including the required dc feed and dc block components) is adopted for all branches, in order to limit the difference in phase rotation versus frequency and to trade off between compactness and bandwidth. The ISMN and IMN topologies, shown in Fig. 9, are optimized separately for each branch, due to the different bias conditions and periphery of the devices. The values of their circuit parameters are reported in Table III. Once the combiner and MNs have been designed, the twostage DPA3W is first simulated with three independent RF inputs whose relative magnitudes and phases are optimized at f 0 , as shown in Fig. 10. The non-linear models of the transistors are used, and the gate bias voltage of each is tuned to ensure the proper turn-on. Despite having in theory as many degrees of freedom as transistors, a unique gate bias voltage is used for the driver and power transistors of the same branch (i.e., which reduces the complexity and still allows to synthesize the required current profiles. The required splitting ratios (P in,M /P in = 0.1, P in,A 1 /P in = 0.22, P in,A 2 /P in = 0.68), and the fact that the linear gain of the Main amplifier chain is around 22 dB, allows to predict an overall gain around 12 dB for the whole two-stage DPA3W. Fig. 11 reports the simulated performance of the two-stage DPA3W at 28 GHz, adopting the device non-linear models. The power gain is estimated assuming an ideal (lossless) input power splitting, for which P in = P in,M + P in,A 1 + P in,A 2 . Thanks to the optimized input driving, the obtained efficiency curve Fig. 11(a) and fundamental current profiles Fig. 11(b) are very close to those predicted by the theory. Indeed, the real part of the impedance Fig. 11(c) and the dynamic load lines Fig. 11(d)-(f) at the intrinsic drain planes of the three final devices confirm that the expected load modulation takes place. The gain of the two-stage DPA3W is around 12 dB in small signal and 10 dB at saturation, as expected, and its saturated output power is approximately 3.5 W. The efficiency peaks are around 30% at OBO, 35% at OBO 2 , and 40% at saturation, respectively. These are compatible with the performance estimated for the selected devices and the combiner losses estimated in Fig. 8(d), which are higher in back-off and lower at saturation.

D. Predriver and Input Splitter
The DPA3W is completed by implementing a three-way analog splitter that feeds the branches with the required power and performs the signal alignment. Furthermore, since the gain Fig. 12. Schematic of the three-way input splitter. estimated for the two-stage DPA is of the order of 10 dB, a predriver stage is inserted in front of the power splitter.
Since the drivers are biased in different classes (M in class AB, A 1 in shallow class C, A 2 in deep class C), and it is likely that bias tuning will be required after fabrication to achieve the desired turn-on of A 1 and A 2 , a non-isolated power splitter is avoided due to the high sensitivity to the drivers input impedance, which may not be accurately predicted by the foundry non-linear model. An isolated power splitter provides a safer alternative, at the expense of additional losses and larger area occupation.
A three-way isolating splitter could be implemented as a cascade of two two-way power splitters, or as a single-stage 1:3 splitter. The latter is chosen to minimize area occupation. A double branchline structure, shown in Fig. 12, can synthesize the desired splitting ratios with reasonable accuracy, while providing output ports isolation of at least 10 dB. Since a 90 • phase shift is present between adjacent output ports, appropriate delay lines have to be inserted on each branch. The circuit parameters are summarized in Table IV, where all the splitter TLs are 90 • at f 0 , the three output ports are matched to 50 , and the input port impedance is 10 . The latter is convenient to simultaneously keep the TLs characteristic impedances within feasible values and ease the design of the OMN of the predriver device (4 × 75 μm), which is implemented with a stub-line topology. The branchline splitter is implemented in semi-lumped form, mainly to favor layout compactness, where the low-impedance TLs are replaced by their π equivalent networks, as done for the combiner and PMN. Finally, the IMN of the predriver is analogous to the IMNs of the A 1 and A 2 drivers, since they are based on the same active device.

IV. FABRICATION AND EXPERIMENTAL RESULTS
The resulting three-stage DPA3W MMIC, shown in Fig. 13, has an area of 3.73 × 4.2 mm 2 . It has been fabricated, mounted on a brass carrier with low-temperature solder paste, and dc and RF probed for the experimental characterization. The adopted dc probes are equipped with capacitors for lowfrequency decoupling.
The DPA3W has been experimentally characterized in the nominal bias point V DD = 20 V for all devices, V, corresponding to an overall quiescent drain current I D,tot = 20 mA.

A. Continuous Wave (CW) Measurements
The CW characterization has been performed with a precalibrated scalar setup. The input and output powers are  Fig. 14(c). Only simulated data are available in this case, since the layout of the combiner does not allow to separate such contributions. The overall agreement of the obtained results proves the effectiveness of the presented design strategy.
Furthermore, the DPA3W maintains a relatively flat response over a 1 GHz frequency band, from 28 to 29 GHz, as shown in Fig. 15. The saturated output power is between 34 and 34.3 dBm, with associated PAE and gain in excess of 20% and around 10 dB. The PAE is in the range 13%-16% both at 6 and 12 dB OBO.
The performance of the DPA3W is summarized and compared to the State Of the Art (SOA) in Table V. The results prove to be competitive over a 1 GHz band, especially in terms of efficiency at deep back-off, although not outperforming twoway DPAs [26], [27] in terms of efficiency at saturation and at 6 dB OBO. Furthermore, the PAE is strongly affected by the complexity in terms of presence/absence of driver stages, and thus by the gain. Single-stage DPAs [28] can achieve a remarkable efficiency even at these frequencies, but inevitably feature a very limited gain.
All in all, the theoretical advantages of a DPA3W at 5G FR2 frequencies may be hindered by the complexity of the architecture, especially to recover the inherently low gain. Therefore, future work will focus on the further simplification of the architecture and minimization of the losses.

B. Modulated Signal Measurements
The DPA3W has then been characterized at 28 GHz under modulated signals excitation to assess its inherent linearity, i.e., without the assistance of digital predistortion. The adopted signal is a 5G NR downlink compliant 64-QAM with 40 MHz instantaneous bandwidth, compatible with the limitations of the available setup. The corresponding PAPR of the signal is 10 dB. The adopted measurement setup includes a Keysight E8267D PSG for the signal generation and up-conversion and a Keysight N9021B MXA as receiver. The baseline   EVM and ACPR measured using an on-wafer thru are <1% and <−48 dBc, respectively.
The linearity requirements of the 3GPP for 64-QAM 5G NR signals [29] (EVM < 8% and ACPR < −28 dBc) are satisfied until an average output power of 17 dBm. At an average output power of 15 dBm, the DPA3W achieves EVM < 5% and ACPR < −32 dBc with associated PAE of 8%.  Fig. 16. At the highest measured average output power of 25 dBm, the DPA3W achieves ACPR < −20 dBc with associated PAE of 14%. Fig. 17 shows the corresponding measured output power spectrum.

V. CONCLUSION
This article has presented the theoretical design equations, a practical design strategy, and the implementation of a DPA3W. Based on the equations, design charts are drawn to explore the available design space. The proposed technique has been experimentally demonstrated by the design, fabrication, and characterization of a DPA3W adopting the WIN Semiconductors' 150 nm gate length GaN-SiC HEMT process. The DPA3W is optimized for 6 and 12 dB efficiency at 28 GHz, targeting 5G applications. The prototype achieves saturated output power in excess of 34 dBm and PAE of the order of 15% from 6 to 12 dB OBO, demonstrating competitive performance compared to the current SOA at similar frequencies. A very good agreement is found between simulations and measurements, thus proving the validity of the approach. A preliminary characterization with a 5G modulated signal has also been reported, demonstrating encouraging results in terms of efficiency-linearity trade-off. Paolo Colantonio (Senior Member, IEEE) received the Laurea degree in electronics engineering and the Ph.D. degree in microelectronics and telecommunications from the University of Rome Tor Vergata, Rome, Italy, in 1994 and 2000, respectively.
He is currently a Full Professor of microwave electronics with the University of Rome Tor Vergata. He is the author or a coauthor of more than 300 scientific articles. He has authored the book High Efficiency RF and Microwave Solid State Power Amplifiers (Wiley, 2009), three book chapters, four contributions to Encyclopedia of RF and Microwave Engineering (Wiley), and one international patent. His research activities are mainly focused on the field of microwave and millimeter-wave electronic, and in particular on the design criteria for non-linear microwaves subsystems and high-efficiency power amplifiers.
Dr. Colantonio has been the Chair of European Microwave Integrated Circuits Conference (EuMIC) 2022. He is currently an Associate Editor of IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS.
Rocco Giofrè (Senior Member, IEEE) received the Ph.D. degree in electronics from the University of Rome Tor Vergata, Rome, Italy, in 2008.
He joined the Department of Electronics Engineering, University of Rome Tor Vergata, in 2009, where he is currently an Associate Professor of electronics. His research activities belong to the microwave and millimeter-wave electronics area ranging from active devices characterization to the design and test of linear and nonlinear circuits and systems. In this wide research area, he is mainly focused on the development of innovative power amplifiers' schemes and architectures with high efficiency and linearity for both ground and space communication systems, including their integration in multifunctional chips such as single-chip front ends. He is involved in many research projects funded by international research agencies, such as the European Space Agency (ESA) and the Research Executive Agency (REA) of the European Commission. He has published more than 190 peer-reviewed articles, two book chapters, and two contributions for the Encyclopedia of Electrical and Electronics Engineering Open Access funding provided by 'Politecnico di Torino' within the CRUI CARE Agreement